The recent miniaturization of DRAM (Dynamic Random Access Memory) cells has been accompanied by the necessity of shortening the gate length of memory cell transistors. However, short channel effects in a transistor become more severe as the gate length is shortened, and drawbacks occur whereby sub-threshold current increases. When the substrate impurity concentration is increased in order to minimize this effect, deterioration of the refresh characteristics in the DRAM is a severe drawback because of increased junction leakage.
A so-called trench-gate transistor (also referred to as a recess-channel transistor) in which a gate electrode is embedded in a groove formed on a silicon substrate has been emphasized as a means of overcoming these drawbacks (see Japanese Laid-open Patent Application Nos. H9-232535, 2001-210801, 2005-142203, H7-066297, and 2004-014696). Using a trench-gate transistor, the effective channel length (gate length) can be physically and adequately maintained, and it is possible to create precision DRAM having a minimum feature size of 90 nm or less.
On the other hand, in DRAM, since there is little need to make the gate length of the transistors in the peripheral circuit region compared with the transistor in the memory cell region, a normal planar transistor is formed in the peripheral circuit region.
Accordingly, trench-gate transistors and planar transistors should be simultaneously formed on a single semiconductor substrate.
However, the thickness of the gate oxide film must be reduced for the sake of low-voltage operation in most of the transistors formed in the peripheral circuit region, whereas a boost voltage is applied to the transistors formed in the memory cell region, and a high breakdown voltage is therefore required. Specifically, a thick gate insulating film is required in the memory cell region.
FIGS. 39 through 44 are used hereinafter to describe a conventional method for providing the memory cell region with a trench-gate transistor in which the gate insulating film is a thick oxide film, and providing the peripheral circuit region with a planar transistor in which the gate insulating film is a thin oxide film. In FIGS. 39 through 44, “region M” indicates the memory cell region, and “region PE” indicates the region provided with a planar transistor that uses a thin oxide film as the gate insulating film in the peripheral circuit region. The peripheral circuit region also includes a region (not shown) in which a power supply circuit and the like are formed, and which is a region other than region PE.
As shown in FIG. 39, a gate trench 202 is formed in region M of a semiconductor substrate 200 whose regions are separated by STI (Shallow Trench Isolation) 201. Although not shown in the drawing, sacrificial oxidation is then performed by thermal oxidation to remove damage and contamination from the etched surfaces inside the gate trench 202, after which a somewhat thick silicon oxide film 203 is formed by thermal oxidation on the entire surface that includes the inner wall of the gate trench 202, as shown in FIG. 40. As shown in FIG. 41, region M is then covered, a resist pattern 204 for exposing region PE is formed, and the silicon oxide film 203 in region PE is removed by wet etching using the resist pattern 204 as a mask. Then, after the resist pattern 204 is removed, the entire surface is again oxidized by thermal oxidation. The silicon oxide film 203 on the surface of the substrate 200 and the inner wall of the gate trench 202 in region M thereby grows thicker, as shown in FIG. 42, yielding a thick oxide film 205t that serves as the gate insulating film of the trench-gate transistor. At the same time, a thin oxide film 205s is formed in region PE to be the gate insulating film of the planar transistor.
A doped silicon film 206 is then formed on the entire surface so as to fill in the gate trench 202, as shown in FIG. 43, and the doped silicon film 206 is patterned in the shape of a gate electrode. The gate electrode 208 of the trench-gate transistor and the gate electrode 207 of the planar transistor are thereby formed, as shown in FIG. 44. Ion implantation is then performed for each semiconductor substrate 200 using the gate electrodes 207 and 208 as masks, source/drain diffusion regions 209 are formed in region PE, and source/drain diffusion regions 210 are formed in region M. A planar transistor having a thick gate insulating film is thereby formed in region PE, and a trench-gate transistor having a thin gate insulating film is formed in region M.
However, the conventional method described above has the following types of drawbacks.
Specifically, the method described above requires at least three thermal oxidation steps to be performed in the gate trench 202 that include sacrificial oxidation, thermal oxidation for forming the silicon oxide film 203, and thermal oxidation for causing the silicon oxide film 203 to grow into the thick oxide film 205t. Oxidation stress inside the gate trench 202 thereby increases, and the DRAM refresh characteristics are adversely affected.
Since the opening of the gate trench 202 becomes narrow as the size of the device is reduced, the oxidation rate inside the gate trench 202 decreases, and the oxidation rate inside the gate trench 202 therefore becomes lower than that of the flat portion (surface of the substrate 200). Therefore, when an attempt is made to form an oxide film in region PE at the same time as an oxide film having the necessary thickness is formed inside the gate trench 202, the oxide film on the surface of region PE becomes too thick. The silicon oxide film 203 on region PE must then be temporarily removed, as shown in FIG. 41.